The present invention relates to a semiconductor device used for a memory cell. The semiconductor memory device of the present invention is used, for example, for a memory cell of a read-only memory (ROM).
There are two prior art methods for forming "ON" or "OFF" states of a memory cell of a ROM. The first method is to change the threshold voltage of a field effect transistor (FET) to correspond to the "ON" or "OFF" state, the second method is to utilize a contact hole in the structure of an FET.
In the first method, the threshold voltage of a metal-oxide semiconductor (MOS) type FET is changed either by changing the thickness of the gate oxide layer or by ion implantation into the channel region. In the former technique, provision of a thick gate oxide layer results in a high threshold voltage, wherein the FET does not become "ON", while provision of a thin layer results in a low voltage, wherein the FET does become "ON". In the latter technique, boron is the type of ion implanted in the channel region to change the conductivity type from p type to p.sup.+ type and, accordingly, to increase the threshold voltage.
As is well known, however, a write-in of the cells of a ROM must, from the viewpoint of convenience to manufacturers and users, be carried out at a relatively later stage in the ROM manufacturing process. For this reason, the above described method of changing the threshold voltage is inappropriate, because the above-described techniques for changing the threshold voltage have to be effected at a relatively early stage in the ROM manufacturing process.
In the second method, a contact hole is formed to connect the source of the substrate and the word line in the vicinity of the gate electrode. Specifically, a window is formed in the oxide layer in the vicinity of the gate electrode.
In such a structure, however, the contact hole must be formed at a certain distance from the gate electrode in order to prevent short-circuits therebetween. Therefore sufficient tolerance must be provided in forming the window in the oxide layer. This increases the length of the n.sup.+ type region of the substrate for the contact hole portion, thereby increasing the size of the FET unit and preventing the realization of a highly integrated device.